The present invention relates to integrated circuit devices and fabrication techniques therefor, and more particularly, to contact structures for integrated circuit devices and methods of fabrication therefor.
Generally, patterns formed in semiconductor devices have decreased in size as the semiconductor devices have become more highly integrated. For example, widths of wirings and intervals between wirings in semiconductor devices have been greatly reduced. In addition, sizes of adjacent structures, as well as the dimensions of bit lines, have been greatly reduced. For example, bit line contacts and self-aligned contact pads have taken on reduced dimensions. Particularly, contacts that connect isolated device regions to one another using a conductive film often consume a considerable area in a semiconductor device because of a need to maintain alignment margins and isolation. As a result, contact size often is a significant factor in determining cell size in a semiconductor memory device, such as a dynamic random access memory (DRAM) device.
As semiconductor manufacturing technology below about 0.25 μm has been developed, conventional methods for forming contacts may not be feasible. In a semiconductor memory device including a plurality of conductive films, interlayer dielectrics are typically interposed between the conductive films. Formation of a contact that electrically connects conductive films to one another generally becomes more difficult as separation between the conductive films increases.
A method for forming a contact using a self-aligned process has been developed in order to reduce an area of a cell in the semiconductor memory device including a repetitive formation of identical patterns and an inadequate design rule. Generally, this conventional method for forming a self-aligned contact uses steps defined by adjacent structures. The contact may have a size that varies in accordance with heights of the adjacent structures, a thickness of an insulation film where the contact is formed, and an etching process used to form the contact. The conventional method for forming a self-aligned contact may be advantageously performed to form a minute contact without requiring precise alignment margin for the contact. A conventional method for forming the self-aligned contact is performed using an etching selectivity between an oxide film and a nitride film during an anisotropic etching process. Examples of such a method are disclosed in Korean Patent Laid Open Publication No. 2001-76166, Japanese Patent Laid Open Publication No. 10-27889, and Korean Patent Laid Open Publication No. 2001-59019.
FIGS. 1A to 1C are cross-sectional views illustrating a method for forming a self-aligned contact according to the disclosure in Japanese Patent Laid Open Publication No. 10-27889.
Referring to FIG. 1A, after an oxide film 15 is formed on a semiconductor substrate 10 having a transistor structure formed thereon, the oxide film 15 is partially etched to form a groove 20 for a bit line having a predetermined dimension. A first metal barrier layer 25 and a first conductive film 30 are successively formed on the oxide film 15 and in the groove 20. The metal barrier layer 25 and the first conductive film 30 are partially etched to form a bit line 35 in the groove 20.
Referring to FIG. 1B, after a nitride capping layer 40 is formed on the bit line 35, the oxide film 15 between the bit lines 35 is etched using a photoresist pattern as an etching mask to form a contact hole 45 adjacent to the bit line 35. Nitride spacers 50 are formed on a sidewall of the bit line 35, on a side portion of the capping layer 40 and on a sidewall of the contact hole 45.
Referring to FIG. 1C, a contact plug 65 is formed between the bit line 35 by forming a second metal barrier layer 55 and a second conductive film 60 in the contact hole 45. Because the contact hole is formed using the capping layer composed of nitride as a hard mask, a size of the contact hole is decreased and a processing margin for opening the contact may not be ensured when a critical dimension (CD) of the bit line is reduced to below about 100 nm. As a result, a void may be formed in the contact plug because the contact hole may not be completely filled up with the conductive material. Additionally, metallic hard polymer may be generated during etching processes for forming the bit line and the contact hole. The metallic hard polymer may cause an electrical short of a semiconductor device, e.g., the metallic hard polymer may form a bridge connecting one bit line to an adjacent bit line or the contact plug.
To overcome the above-described problems, a method for forming a bit line and a capacitor contact using a damascene process is disclosed in U.S. Pat. No. 6,344,389 (issued to Gary B. Bronner et. al.), Korean Patent Laid Open Publication No. 2001-8589 and Korean Patent Laid Open Publication No. 2001-55683.
FIGS. 2A to 2E are cross-sectional views illustrating a method for manufacturing a semiconductor device having a bit line and a capacitor contact using a damascene process according to the disclosure in U.S. Pat. No. 6,344,389.
Referring to FIG. 2A, an isolation film 105 is formed on a semiconductor substrate 100 using a shallow trench isolation (STI) process to define a cell region and a peripheral circuit region in the semiconductor substrate 100. After a protection layer 115 is formed to enclose a transistor 110 on the semiconductor substrate 100, a first insulation film 120 is formed on the semiconductor substrate 100. The first insulation film 120 may include silicon oxide or silicon nitride.
After an upper portion of the first insulation film 120 is planarized using a chemical-mechanical polishing (CMP) process, the first insulation film 120 is partially etched using a photolithography process to form holes (not shown) that expose source/drain regions 125 of the transistors 110. When the holes are filled with conductive materials like polysilicon or tungsten silicide, a self-aligned contact (SAC) pad 130 of a bit line and a SAC pad 135 of a capacitor are formed.
Referring to FIG. 2B, after an interlayer dielectric (ILD) 140 is formed on the first insulation film 120 including the SAC pads 130 and 135 of the bit line and the capacitor, the interlayer dielectric 140 is etched to form a capacitor contact hole (not shown) exposing the SAC pad 135 of the capacitor. The capacitor contact hole is partially filled with a conductive material like polysilicon or tungsten silicide to from a capacitor contact 145. A protection layer 150 is formed on the capacitor contact 145. A portion of the ILD 140 adjacent to the capacitor contact 145 is partially etched to form a trench 155. Spacers 160 are formed on sidewalls of the trench 155 of the ILD 140. The spacers 160 may include an insulation material, such as silicon nitride.
Referring to FIG. 2C, a bottom of the trench 155 is partially etched to form a bit line contact hole (not shown) exposing the SAC pad 130 of the bit line. A conductive material is formed in the trench 155. After the conductive material is polished in a damascene process, a dry etching process or a wet etching process is performed to form a bit line contact 165 in the bit line contact hole and a bit line 170 having a predetermined thickness is formed in the trench 155.
Referring to FIG. 2D, a second insulation film 175 is formed on the ILD 140, the capacitor contact 145 and the bit line 170. The second insulation film 175 is partially etched to form an opening 180 exposing an upper portion of the capacitor contact 145. Referring to FIG. 2E, a portion of the protection layer 150 and the upper portion of the capacitor contact 145 are removed through the opening 180. A bottom electrode, a dielectric region and a top electrode are successively formed in the opening 180, thereby forming a capacitor 185. Portions of the second insulation film 175 and the ILD 140 around the capacitor 185 are etched using a CMP process to form a semiconductor device having a capacitor-over-bit line (COB) structure.
In the above-described method for forming the semiconductor device, a parasitic capacitor including the bit line, the spacer and the contact plug may be formed. A capacitance of the parasitic capacitor may be relatively high because the nitride spacer has a relatively large dielectric constant of more than about 8. Consequently, the transient response of the semiconductor device may be reduced and a capacitance of the capacitor may be reduced. Additionally, the processes for forming and etching the protection layer may increase manufacturing cost and manufacturing time because the protection layer is removed with a portion of the capacitor contact after the protection layer is formed on the capacitor contact. Furthermore, metal hard polymers may be generated during etching of the protection layer, and these metal hard polymers may cause failure of the semiconductor device. The metal hard polymers may be more frequently generated when the bit line is formed by etching the conductive material.